1. Technical Field
The embodiment described herein relate to a semiconductor integrated circuit (IC) apparatus and a method thereof and, more particularly, to a duty cycle correcting circuit included in a semiconductor IC apparatus and a method of correcting a duty cycle of a clock signal.
2. Related Art
In general, semiconductor IC apparatuses, such as synchronous dynamic random access memory (SDRAM) apparatus, have increased operational speeds by operating using clock signals. For example, a semiconductor IC apparatus includes a clock buffer and buffers an external clock signal to use it inside. In some cases, the semiconductor IC apparatus uses a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit to generate and use an internal clock signal where a phase difference with the external clock signal is corrected. In the internal clock signal used in the semiconductor IC apparatus, a ratio between a high level interval and a low level interval, i.e., a duty ratio, is preferably maintained at a predetermined ratio of 50:50. However, since the semiconductor IC apparatus includes numerous delay elements, the duty ratio of the internal clock signal may easily vary.
Due to the high-speed operations of semiconductor IC apparatuses, utilization of a clock signal has increased, wherein a clock having a stable duty ratio is required. Accordingly, each semiconductor IC apparatus includes a duty cycle correcting circuit to stabilize a duty ratio of a clock signal. The duty cycle correcting circuit becomes increasingly important to utilize a stable clock signal during high speed operation of the semiconductor IC apparatus.
Types of duty cycle correcting circuits may be classified into analog-type and digital-type. The digital-type duty cycle correcting circuit is advantageous in terms of low use of occupied area of the semiconductor IC apparatus and high operational speeds. The digital-type duty cycle correcting circuit includes multi-stage drivers, and changes driving abilities of the drivers in response to a digital code, and adjusts a duty ratio of a clock signal. For example, in a two-stage driver, a driving ability of a pull-up section of a driver of a first stage and a driving ability of a pull-down section of a driver of a second stage are adjusted, thereby changing a width of a low level interval of a clock signal. Accordingly, the digital code is a signal that is generated by generating a binary code using a general counter and decoding the binary code. Thus, when a logical value of the digital code is changed, the driving abilities of the individual drivers of the two stages are sequentially changed.
The duty cycle correcting circuit is configured such that a driving ability of one of a plurality of drivers is first changed in response to the digital code, and driving abilities of the other drivers are also changed. For example, the duty cycle correcting circuit is operated such that the pull-up section of the driver of the first stage and the pull-down section of the driver of the second stage are set to have maximum driving abilities on the basis of a default value of the digital code, and the driving ability of the pull-up section of the driver of the first stage is gradually decreased and minimized. In addition, the driving ability of the pull-down section of the driver of the second stage is gradually decreased and minimized, when the digital code is changed. However, if the driving ability of the pull-up section of the driver of the first stage is minimized, then the driving ability of the entire driver of the first stage is decreased, and a fan-out difference increases between the drivers of the two stages. As a result, all of the drivers can be erroneously operated. That is, the duty cycle correcting circuit is designed in consideration of only a duty cycle correction operation without considering fan-out between the drivers. For this reason, stability of the operation is lowered.